ELEC4720 – Programmable logic design

ELEC4720 – Programmable logic designAssignment 2• This assignment consists of three steps:2.1 First you will design the instruction set architecture of a microprocessor. You will…

ELEC4720 – Programmable logic designAssignment 2• This assignment consists of three steps:2.1 First you will design the instruction set architecture of a microprocessor. You will alsodevelop the logic circuit to implement your design.2.2 Then you will implement your design on DE2 board. At this stage you will implementa single cycle processor.2.3 In the final stage you will design a pipelined processor which is about 5 times fasterthan the single cycle design.Assignemt 2 is a group assignment. Each group should consist of two students.You are welcome to form your own group. It is fine if you prefer to work alone.• This assignment is due on the last day of the exam period.• Submission should consist of a report and your source code:{ A report. The report should explain your insruction set architecture, circuit diagrams,and necessary logic derivations (particularly for various control signals) Submit the pdffile via the link provided in blackboard.{ The source code must consist of the .sv implementation of the CPU hardware andassociated test circuit on DE2 board. In addition you should also supply the testprograms. As usual, copy and paste everything in a .txt file and submit via blackboard.• You must demonstrate the hardware implementation of your design before thedeadline. Please send an email to the course coordinator when you are ready.• You are encouraged to complete and get individual parts marked as you completethem. Please contact your lab demonstrator if you like to do so.Part 2.1 – Aim to complete this by the end of week 9.1. Design the instruction set architecture of a single cycle processor with 18 bit wide instructions,and data-word width of your choice. In your report show the hardware implementation detailsof the processor. In particular, provide the• Instruction set along with the binary codes• Instruction encoding/decoding logic• Discuss various tradeoffs made in your design to optimize the following:{ Instruction coverage{ Dataword width,{ Number of registers,{ Memory adressing scheme (byte or word addressable, base/offset based addressing){ Memory address and offset range1{ Jump offset range{ Branch offset range• Show the data path needed to implement your design• Discuss the the control signals and their logicNotes.The complexity and the effort needed depends significantly on the data word width of theprocessor. This the marks automatically depend on the data word width. You should aim for atleast 16 bit wide data words.The utility and efficiency of a processor depends significantly on the number of registers. Henceone prefers to have as many resgisters as possible. However, having more than 32 registers typicallyslows down a processor due to the increase in the address decoding time.Similarly, it is desirable to have large memory offset range, jump offset range and branch offsetrange.Aim to implement as many instructions from the standard MIPS instruction set as possible,and justify why it is not required/possible to implement more.Marking criterion.The mark is allocated as follows:1. Description of the instruction set (5)2. Instruction encoding/decoding logic (5)3. Rationale behind the design and associated design trade-offs (12)4. Instruction coverage (28)• ALU instructions with register operands (4)• Multiplication/Division instructions with register operands (4)• Shift instructions with register operands (4)• ALU instructions involving constant operands (4)• Branch instructions (4)• Jump instructions (4)• Memory read and write instructions (4)5. Description of datapath, control signals and control signals’ logic (3+3+4 = 10)Note: The marks in points 2, 4 and 5 will depend on the simplicity of the hardwareimplementation needed to support the designed instruction set. If the hardwareneeded involves circuits with large delay, then the processor throughput decreases.That is considered as a serious demerit.2Part 2.2 – Single cycle implementation (aim to complete this by the end of week 11)1. Design and implement a single cycle processor with 18 bit wide instructions, and data-wordwidth of your choice. In addition, test your processor on DE2 board using one or moreappropriate test programs. Together these programs should be rich enough in the sense that• it should include the common programming language constructs like standard arithmetic, logic, and shift oprtations, conditional statements (if-then-else type), loops, etc.• it should be sufficient to demonstrate that all the main hardware components of yourdesign is working properlyIf your design for this Part is different from your design in Part 2.1, then please update yourreport with the• Instruction set along with the binary codes• Instruction encoding/decoding logic• Discuss various tradeoffs made in your design to optimize the following:{ Instruction coverage{ Dataword width,{ Number of registers,{ Memory adressing scheme (byte or word addressable, base/offset based addressing){ Memory address and offset range{ Jump offset range{ Branch offset range• Show the data path needed to implement your design• Discuss the the control signals and their logicMarking criterion.• Processor coverage (28){ ALU instructions with register operands (3){ Multiplication/Division instructions with register operands (3){ Shift instructions with register operands (3){ ALU instructions involving constant operands (4){ Branch instructions (5){ Jump instructions (4){ Complexity of memory read and write instruction implementation (6)• Testing (22){ Capability of the test methodology to ensure the bug-free hardware (7)3{ Final demo program on DE2 board (15)• Speed (5){ The mark will depend on how fast your processor can be clocked on DE2 board.Note:• Please maintain a log of all the test programs and strategies used during the course ofhardware development. This should also include the test programs used for testing variousparts of the design while the hardware is being developed. You are welcome to attach thislog as an appendix to your report.• If you are unable to demonstrate the CPU on the DE2 board then you will not get the fullmarks. The mark will depend on our examination of your code, and testing on modelsim.Tips.• It will be very convenient to have an assembler to translate your assemblylabguage code into binary machine language code. If possible, then write aC/Java/etc assmebler program for your instruction set architecture. Having anassembler saves a huge amount of work during the testing phase.• In the implementation phase use step by step testing. First build the subprocessor implementing the R-type instructions. This should not take you long, and most of the buildingblocks are already available from assignment 1. Test it extensively. Then keep enhancingthe processor by adding additional functionalities step by step as we develop MIPS-32 architecture in the lecture notes. Do extensive testing in each steps. Document your testingmethods and save your test codes at each step.• Don’t forget to backup your hardware design code after you have successfullycompleted a logical step.• It will be easy to work on modelsim in the development phase. However when you thinkyour design is complete and is working then you need to port your code to the DE2 board,and use the peripherals in the DE2 board to demonstrate the processor via an appropriatetest program.• In order to interface the processor with the peripherals on the DE2 board, youcan use memory mapped input output, where the input-output ports have someaddress and you use memory read-write instructions for input/output.• While working on the DE2 board start with a slow clock like 1 Hz. Then gradually increasethe clock speed and test how fast you can clock your processor. For a good design you shouldbe able to clock your CPU with a 10 MHz (or above) clock.4Part 2.3 – Pipelined design1. Design and implement a 5 stage pipelined processor with 18 bit wide instructions, and dataword width of your choice. In addition, test your processor on DE2 board using one or moreappropriate test programs. Together these programs should be rich enough in the sense that• it should include the common programming language constructs like standard arithmetic, logic, and shift oprtations, conditional statements (if-then-else type), loops, etc.• it should be sufficient to demonstrate that all the main hardware components of yourdesign is working properlyIf your design for this part is different from your design in Part 2.2, then please update yourreport with the• Instruction set along with the binary codes• Instruction encoding/decoding logic• Discuss various tradeoffs made in your design to optimize the following:{ Instruction coverage{ Dataword width,{ Number of registers,{ Memory adressing scheme (byte or word addressable, base/offset based addressing){ Memory address and offset range{ Jump offset range{ Branch offset range• Show the data path needed to implement your design• Discuss the the control signals and their logicMarking criterion.• Processor coverage (14){ ALU instructions with register operands (2){ Multiplication/Division instructions with register operands (2){ Shift instructions with register operands (2){ ALU instructions involving constant operands (2){ Branch instructions (2){ Jump instructions (2){ Complexity of memory read and write instruction implementation (2)• Hazard management (15){ Read after write hazard (5)5{ Memory load hazard (5){ Branch hazard (5)• Testing (21){ Capability of the test methodology to ensure the bug-free hardware (7){ Final demo program on DE2 board (14)• Speed (10){ The mark will depend on how fast your processor can be clocked on DE2 board.Note:• Please document all the test programs and strategies used during the course of hardwaredevelopment. This should also include the test programs used for testing various parts ofthe design while the hardware is being developed.• If you are unable to demonstrate the CPU on the DE2 board then you will not get the fullmarks. The mark will depend on our examination of your code, and testing on modelsim.• While working on the DE2 board start with a slow clock like 1 Hz. Then gradually increasethe clock speed and test how fast you can clock your processor. For a good design you shouldbe able to clock your CPU with a 50 MHz clock.6

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